1. Field of the Invention
The present invention relates to a multilayer wiring board suitable for providing semiconductor chip mounting boards, motherboards, substrates for probe cards, and so on.
2. Description of the Related Art
In recent years, there is an increasing requirement for higher performance and smaller size in electronic products. Accordingly, there is an ever-accelerating trend toward high density mounting of electronic parts incorporated in these electronic products. In an effort to meet such a high density mounting, semiconductor chips are often surface-mounted as bare chips onto the wiring board (flip-chip mounting). Changes have also been observed with respect to the wiring board for mounting these semiconductor chips. Specifically, as a semiconductor chip has a larger number of connector pins, a multilayer wiring board is preferably used due to the advantage in high density wiring. Semiconductor packages, which may contain these semiconductor chips and wiring boards, are necessary parts in electronic circuits, and so are mounted further on a motherboard. The motherboard can also be a multilayer wiring board in order to achieve desirable high density wiring. In response to the high pin-count trend in devices and chips multilayer substrates are also used in probe cards for inspection purposes.
In the flip-chip mounting, an under filler is generally used to fill a gap between the wiring board and the semiconductor chips mounted thereon. If the under filler is not used, electrical connection between the wiring board and the semiconductor chips is often not desirably reliable because of difference in thermal expansion coefficient between the wiring board and the semiconductor chips. Typically, a semiconductor chip made of common row materials has a thermal expansion coefficient of about 3.5 ppm/K along the plane of surface. On the other hand, a typical wiring board including a core substrate provided by a glass epoxy substrate has a thermal expansion coefficient of about 12 through 20 ppm/K along the plane of surface. Thus, the difference in the thermal expansion coefficient between the two is relatively large. For this reason, change or repeated changes in ambient temperature can easily create stress in electrical connections between the wiring board and the semiconductor chips. When the stress at the electrical connection exceeds a certain limit, the electrical connection, or a boundary surface between bumps on the semiconductor chip and electrode pads on the wiring board, can easily crack or separate from each other. The under filler applied between the semiconductor chip and the wiring board during the flip-chip mounting buffers the stress which develops at the electric connection. Due to this stress reduction capability, incidence of cracking and separation is decreased and connection reliability in the flip-chip mounting is increased.
However, when a large semiconductor chip is mounted on a wiring board, the stress reduction by the under filler alone is often not sufficient for ensuring desirable reliability. This is because the absolute amount of thermal expansion difference between the semiconductor chip and the wiring board resulting from the difference in the thermal expansion coefficient of the two components increases with an increasing size of the chip. A larger thermal expansion difference creates a greater stress at the electrical connection. Such a problem can also develop when a semiconductor wafer or a relatively large semiconductor chip is mounted on a probe card for performance inspection.
The above problem resulting from the difference in the thermal expansion coefficient between the wiring board and the semiconductor chip could be eliminated or reduced by using a wiring board having a small thermal expansion coefficient. Wiring substrates having a small thermal expansion coefficient are conventional. There is known a wiring board using a core substrate provided by a metal which has a small thermal expansion coefficient. The metal core substrate is generally made of aluminum, copper, silicon steel, nickel-iron alloy, CIC (a clad material having a structure of copper/Inver/copper) and so on. A wiring board including a copper core substrate is disclosed in the Japanese Patent Laid-Open 2000-138453 for example. However, all of these metals are considerably heavy, having large specific gravity values, and make the resulting wiring board disadvantageously heavy. In addition, metal core substrates have poor machinability in micro machining processes, and often difficult to form minute holes, to make into a thin laminate, and so on.
There is another known method for reducing thermal expansion in the wiring board. The method uses carbon material. Such a technique is disclosed in the Japanese Patent Laid-Open 60-140898, the Japanese Patent Laid-Open 11-40902, and the Japanese Patent Publication 2001-332828 for example.
The Japanese Patent Laid-Open 60-140898 discloses a wiring board of a multilayer structure in which an insulating graphite layer including a carbon fiber sheet and a wiring layer of copper are alternated in lamination. The thermal expansion coefficient of this wiring board is small due to the graphite layers. A problem, however, is that the multilayer structure in such a wiring board is formed by so-called single step pressing method, and it is known that formation of a multi-layered micro-wiring structure and therefore formation of fine-pitched electrodes for external connection is difficult to achieve by this method. For this reason, the wiring board disclosed in the Japanese Patent Laid-Open 60-140898 is not suitable for mounting or installing semiconductor chips having external connection electrodes formed at a fine pitch.
The Japanese Patent Laid-Open 11-40902 discloses a wiring board of a multilayer structure in which a core substrate including a carbon fiber sheet has two surfaces each laminated with an insulating layer of a prepreg which contains glass fiber, and a layer of copper wiring. The thermal expansion coefficient of this wiring board is small since the core substrate includes a carbon fiber sheet. However, according to the Japanese Patent Laid-Open 11-40902, the multilayer structure in such a multilayer wiring board is formed by a single step pressing method. For this reason, the wiring board disclosed in the Japanese Patent Laid-Open 11-40902 is not suitable for mounting or installing semiconductor chips having external connection electrodes formed at a fine pitch.
The Japanese Patent Publication 2001-332828 discloses a wiring board of a multilayer structure in which a core substrate including a carbon-containing fibers has two surfaces each laminated with an insulating layer of a prepreg which does not contain glass fiber, and a layer of copper wiring. However, there is a considerably large difference in thermal expansion coefficient between the core substrate which includes the carbon-containing fibers and the prepreg which does not include glass fibers. When there is a large difference in thermal expansion coefficient, the core substrate and the insulating layer can separate easily, and if the separation occurs between the core substrate and the insulating layer, the wiring can be subjected to an undesirably large stress and eventually cut. Therefore, according to the technique disclosed in the Japanese Patent Laid-Open 2001-332828, it is sometimes difficult to appropriately obtain a wiring board which has a small, overall thermal expansion coefficient.